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62707 ms im b8-9164 / 80102 as (ot) no.7256-1/14 LB11870 overview the LB11870 is a three-phase brushless motor driver developed for driving the motors used with the polygonal mirror in laser printers and plain paper copiers. it can implement, with a single ic chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. the LB11870 can implement motor drive with minimal power loss due to its use of direct pwm drive. functions ? three-phase bipolar drive ? direct pwm drive ? includes six high and low side diodes on chip. ? output current control circuit ? pll speed control circuit ? phase lock detection output (with masking function) ? includes current limiter, thermal protection, rotor constrai nt protection, and low-voltage protection circuits on chip. ? deceleration type switching circuit (free running or reverse torque) ? pwm oscillator ? power saving circuit ordering number : en7256a monolithic digital ic for polygonal mirror motors three-phase brushless motor driver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LB11870 no.7256-2/14 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc max 30 v output current i o max t 500ms *1 2.3 a allowable power dissipation 1 pd max1 independent ic 0.85 w allowable power dissipation 2 pd max2 mounted on a circuit board *2 1.72 w operating temperature topr -20 to +80 c storage temperature tstg -55 to +150 c note *1: be sure to perform derating from the standard value by 20% or more before use. note *2: mounted on a specified board: 114.3mm 76.1mm 1.6mm, glass epoxy allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc 9.5 to 28 v 5v constant voltage output current ireg 0 to -20 ma ld pin applied voltage vld 0 to 28 v ld pin output current ild 0 to 15 ma fgs pin applied voltage vfg 0 to 28 v fgs pin output current ifg 0 to 10 ma electrical characteristics at ta = 25 c, v cc = vm = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 16 21 ma supply current 2 i cc 2 in stop mode 3.5 5.0 ma [5v constant voltage output circuit] output voltage vreg 4.65 5.0 5.35 v voltage regulation vreg1 v cc =9.5 to 28v 80 130 mv load regulation vreg2 i o =-5 to -20ma 10 60 mv temperature coefficient vreg3 design target value* 0 mv/ c [output block] output saturation voltage 1 v o sat1 i o =0.5a, v o (sink)+v o (source) 1.9 2.4 v output saturation voltage 2 v o sat2 i o =1.2a, v o (sink)+v o (source) 2.6 3.2 v output leakage current i o leak 100 a lower diode forward voltage 1 vd1-1 id=-0.5a 1.0 1.3 v lower diode forward voltage 2 vd1-2 id=-1.2a 1.4 1.8 v upper diode forward voltage 1 vd2-1 id=0.5a 1.2 1.6 v upper diode forward voltage 2 vd2-2 id=1.2a 1.9 2.4 v [hall amplifier block] input bias current ihb -2 -0.5 a common-mode input voltage range vicm 0 vreg-2.0 v hall input sensitivity 80 mvp-p hysteresis width v in (ha) 15 24 42 mv input voltage: low to high vslh 12 mv input voltage: high to low vshl -12 mv [fg schmitt block] input bias current ib(fgs) -2 -0.5 a common-mode input voltage range vicm(fgs) 0 vreg-2.0 v input sensitivity v in (fgs) 80 mvp-p hysteresis width v in (fgs) 15 24 42 mv input voltage: low to high vslh(fgs) 12 mv input voltage: high to low vshl(fgs) -12 mv *: these value are design guarantee values, and are not tested. continued on next page.
LB11870 no.7256-3/14 continued from preceding page. ratings parameter symbol conditions min typ max unit [pwm oscillator] high-level output voltage v oh (pwm) 2.65 2.95 3.25 v low-level output voltage v ol (pwm) 0.9 1.2 1.5 v external capacitor charge current ichg vpwm=2v -60 -45 -30 a oscillator frequency f(pwm) c=680pf 34 khz amplitude v(pwm) 1.45 1.75 2.05 vp-p [fgs output] output saturation voltage v ol (fgs) ifgs=7ma 0.15 0.5 v output leakage current il(fgs) v o =v cc 10 a [csd oscillator circuit] high-level output voltage v oh (csd) 3.2 3.5 3.8 v low-level output voltage v ol (csd) 0.9 1.1 1.3 v amplitude v(csd) 2.15 2.4 2.65 vp-p external capacitor charge current ichg1 -13.5 -9.5 -5.5 a external capacitor charge current ichg2 6 10 14 a oscillator frequency f(csd) c=0.068 f 29 hz [phase comparator output] high-level output voltage vpdh i oh =-100 a vreg-0.2 vreg-0.1 v low-level output voltage vpdl i ol =100 a 0.2 0.3 v output source current ipd+ vpd=vreg/2 -0.5 ma output sink current ipd- vpd=vreg/2 1.5 ma [lock detection output] output saturation voltage v ol (ld) ild=10ma 0.15 0.5 v output leakage current il(ld) v o =v cc 10 a [error amplifier block] input offset voltage v io (er) design target value* -10 10 mv input bias current ib(er) -1 1 a output h level voltage v oh (er) i oh =-500 a vreg-1.2 vreg-0.9 v output l level current v ol (er) i ol =500 a 0.9 1.2 v dc bias level vb(er) -5% vreg/2 5% v [current limiter circuit] drive gain 1 gdf1 when the phase is locked 0.4 0.5 0.6 deg drive gain 2 gdf2 when not locked 0.8 1.0 1.2 deg limiter voltage vrf v cc -vm 0.45 0.5 0.55 v [thermal shutdown operation] thermal shutdown operating temperature tsd design target value* (junction temperature) 150 175 c hysteresis width tsd design target value* (junction temperature) 40 c [low-voltage protection] operating voltage vsd 8.1 8.45 8.9 v hysteresis width vsd 0.2 0.35 0.5 v *: these value are design guarantee values, and are not tested. continued on next page.
LB11870 no.7256-4/14 continued from preceding page. ratings parameter symbol conditions min typ max unit [cld circuit] external capacitor charge current icld -6 -4.3 -3 a operating voltage v h (cld) 3.25 3.5 3.75 v [clk pin] external input frequency fi(clk) 0.1 10 khz high-level input voltage v ih (clk) 3.5 vreg v low-level input voltage v il (clk) 0 1.5v input open voltage v io (clk) vreg-0.5 vreg v hysteresis width v is (clk) 0.35 0.5 0.65 v high-level input current i ih (clk) vclk=vreg -10 0 10 a low-level input current i il (clk) vclk=0v -280 -210 a [s/s pin] high-level input voltage v ih (ss) 3.5 vreg v low-level input voltage v il (ss) 0 1.5v input open voltage v io (ss) vreg-0.5 vreg v hysteresis width v is (ss) 0.35 0.5 0.65 v high-level input current i ih (ss) vs/s=vreg -10 0 10 a low-level input current i il (ss) vs/s=0v -280 -210 a [brsel pin] high-level input voltage v ih (brsel) 3.5 vreg v low-level input voltage v il (brsel) 0 1.5v input open voltage v io (brsel) vreg-0.5 vreg v high-level input current i ih (brsel) v brsel =vreg -10 0 10 a low-level input current i il (brsel) v brsel =0v -220 -160 a package dimensions unit : mm (typ) 3278 sanyo : hssop48(375mil) 17.8 0.2 10.5 7.9 0.65 0.2 (6.2) (0.45) (4.9) 0.1 2.4 max (2.2) 0.65 1.3 1.5 124 48 25 ilb01545 2.0 0.8 1.6 1.2 0.4 0 100 80 60 40 20 0 -20 0.85w 0.476w 0.963w 1.72w mounted on a board (114.3 76.1 1.6mm, glass epoxy) pd max - ta ambient temperature, ta - c power dissipation, pd max - w independent ic
LB11870 no.7256-5/14 pin assignment three-phase logic truth table (in = [h] indicates a conditi on in which: in+ > in?) in1 in2 in3 out1 out2 out3 h l h l h m h l l l m h h h l m l h l h l h l m l h h h m l l l h m h l LB11870 47 vreg nc 46 nc out3 44 43 42 41 40 39 48 36 35 34 33 31 30 29 28 27 nc nc nc vcc2 s/s clk brsel ph fgs ld nc nc cld 13 14 15 16 17 18 19 20 21 pd frame nc ei gnd1 fgin? pwm gnd2 fgin+ frame 9 8 7 6 5 4 3 2 1 in3? nc in2? in2+ out1 nc in3+ nc out2 10 38 22 37 vcc1 nc fc nc gnd3 nc 11 12 23 24 26 25 32 45 vm1 vm2 csd fgfil eo toc in1? in1+
LB11870 no.7256-6/14 block diagram and application circuit example ? + hall logic hall hys amp pwm osc brsel s/s logic comp tsd vreg clk ld pll fg filter ? + in2+ in2? in3+ gnd1 in3? pwm s/s vreg vm1 fgin+ fgin? ld eo ei pd toc vreg vcc2 brsel csd in1+ in1? clk driver out1 out2 out3 gnd3 vreg fgs vcc rf peak hold curr lim cont amp ph fc vreg vreg count csd osc gnd2 ldmask cld fgfil vm2 vcc1
LB11870 no.7256-7/14 pin functions pin no. symbol pin description equivalent circuit 3 1 46 out1 out2 out3 motor drive output 44 gnd3 output block ground 37 38 vm1 vm2 output block power supply and current detection. insert the resistor rf between this pin and v cc 1. the output current will be limited to the current value i out = vrf/rf. 39 v cc 2 upper diode cathode connection. short this pin to v cc 1. 11 12 9 10 6 8 in1+ in1- in2+ in2- in3+ in3- hall element inputs. the high state is when in + is greater than in-, and the low state is the reverse. an amplitude of at least 100mvp-p (differential) is desirable for the hall element signal inputs. if noise on the hall signals is a problem, insert capacitors between the in+ and in- inputs. 13 14 fg in + fg in - fg input. if noise on the fg signal input is a problem, connect a filter consisting of either a capacitor or a capacitor and a resistor. 15 gnd1 control circuit block ground 16 gnd2 subgnd pin 17 pwm sets the pwm oscillator frequency. insert a capacitor between this pin and ground. the pwm oscillator frequency is set to about 34khz when a 680pf capacitor is used. continued on next page. 1 3 46 300 44 37 v cc 1 38 39 vreg 300 8 300 11 9 6 12 10 vreg 300 14 300 13 vreg 2k 200 17
LB11870 no.7256-8/14 continued from preceding page. pin no. symbol pin description equivalent circuit 19 fc frequency characterist ics correction for the current control circuit. insert a capacitor (about 0.01 to 0.1 f) between this pin and ground. the output duty is determined by comparing the voltage on this pin to the pwm oscillator waveform. 21 pd phase comparator output. the phase error is converted to a pulse duty and output from this pin. 22 ei error amplifier input. 23 eo error amplifier output. 24 toc torque command voltage input. this pin is normally connected to the eo pin. when the toc voltage falls, the lower output transistor on duty is increased. continued on next page. vreg 300 19 21 vreg 300 vreg 300 22 vreg 300 24 vreg 23 40k
LB11870 no.7256-9/14 continued from preceding page. pin no. symbol pin description equivalent circuit 25 fgfil fg filter connection. if noise on the fg signal input is a problem, insert a capacitor (up to about 2200pf) between this pin and ground. 26 csd sets the rotor constraint protection circuit operating time and the initial reset pulse. a protection operating time of about 8 seconds can be set by insert a capacitor of about 0.068 f between this pin and ground. if the rotor constraint protecti on circuit is not used, insert a resistor and a capacitor in parallel between this pin and ground. (values: about 220k and 4700pf) 27 cld sets the phase lock state signal mask time. a mask time of about 90ms can be set by inserting a capacitor of about 0.1 f between this pin and ground. leave this pin open if masking is not required. 28 fgs fg schmitt output. 29 ld phase lock state detection output. this output goes to the on state (low level) when the phase is locked. continued on next page. 25 vreg vreg 300 26 vreg 27 300 vreg 28 vreg 29
LB11870 no.7256-10/14 continued from preceding page. pin no. symbol pin description equivalent circuit 32 s/s start/stop control input. low: 0 to 1.5v high: 3.5v to vreg hysteresis: 0.5v low: start. this pin goes to the high level when open. 33 clk clock input. low: 0 to 1.5v high: 3.5v to vreg hysteresis: 0.5v f clk = 10khz (maximum) if noise is a problem, use a capacitor to remove that noise at this input. 34 brsel deceleration switching control input. low: 0 to 1.5v high: 3.5v to vreg this pin goes to the high level when open. low: reverse torque control, high: free running. an external schottky barrier diode is required on the output low side if reverse torque control is used. 35 ph rf waveform smoothing. if noise on the rf waveform is a problem, insert a capacitor between this pin and ground. continued on next page. vreg 22k 2k 32 vreg 22k 2k 33 vreg 30k 2k 34 vreg 500 35
LB11870 no.7256-11/14 continued from preceding page. pin no. symbol pin description equivalent circuit 36 vreg stabilized power supply output (5v output). insert a capacitor of about 0.1 f between this pin and ground for stabilization. 40 v cc 1 power supply. insert a capacitor of at least 10f between this pin and ground to prevent noise from entering the ic. 2, 4, 5 7, 18 20, 30 31, 41 42, 43 45, 47 48 nc since these pins are not connected to the ic internally, they can be used for wiring connections. frame connect this pin to ground. overview of the LB11870 1. speed control circuit this ic adopts a pll speed control technique and provides stable motor operation with high precision and low jitter. this pll circuit compares the phase error at the edges of the clk signal (falling edges) and fg signal (falling edges on the fgin+ and fgs signals), and the ic uses the detected error to control motor speed. during this control operation, the fg servo fre quency will be the same as the clk frequency. f fg (servo) = f clk 2. output drive circuit to minimize power loss in the output circuits, this ic ad opts a direct pwm drive tech nique. the output transistors are always saturated when on, and the ic adjusts the motor drive output by changing the output on duty. the low side output transistor is used for the output pwm switching. both the high and low side output diodes are integrated in the ic. however, if reverse torque control mode is selected for use during deceleration, or if a large output current is used and problems occur (suc h as incorrect operation or waveform disruption due to low side kickback), a schottky diode should be inserted between out and ground. also, if it is necessary to reduce ic heatin g during steady-state (constant speed) opera tion, it may be effective to insert a schottky diode between v cc and out. (this is effective because the load associated with the regenerative current during pwm switching is born not by the on-chip diode but by the external diode.) 3. current limiter circuit the current limiter circuit limits the peak level of the curre nt to a level determined by i = vrf/rf (where vrf = 0.5v (typical) and rf is the value of the current detec tion resistor). the current limiter operates by reducing the output on duty to suppress the current. the current limiter circuit detects the reve rse recovery current of the diode due to pwm operation. to assure that the current limiting function does not malfunctio n, its operation has a delay of about 2 s. if the motor coils have a low resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be rapid. the delay in this circuit means that at such times the current limiter circuit may operate at a point well above the set current. designers must take this increase in the current due to the delay into account when setting the current limiter value. 36 v cc
LB11870 no.7256-12/14 4. power saving circuit this ic goes into a power sa ving state that reduces the cu rrent drain in the stop state. the power saving state is implemented by removing the bias current from most of the circuits in the ic. however, the 5v regulator output is provided in the power saving state. 5. reference clock care must be taken to assure that no chattering or other noise is present on the externally input clock signal. although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. if the ic is set to the start state when the reference clock sign al is not present, if the rotor constraint protection circuit is used, the motor will turn somewhat and then motor drive will be shut off. however, if the rotor constraint protection circuit is not used, and furthe rmore reverse torque control mode is se lected for deceleration, the motor will be driven at ever increasing speed in the reverse directio n. (this is because the rotor constraint protection circuit oscillator signal is used for clock cutoff protection.) applications must implement a workaround for this problem if there is any possibility whatsoever for it to occur. 6. notes on the pwm frequency the pwm frequency is determined by the value of the capacitor c (i n f) connected to the pwm pin. f pwm 1 / (43000 c) if a 680pf capacitor is used, the circuit will oscillate at about 34khz. if the pwm frequency is too low, the motor will emit switching noise, and if it is too high, the power loss in the output will be excessive. a pwm frequency in the range 15 to 50khz is desirable. to minimize the influence of the output on this circuit, the ground lead of this capacitor should be connected as cl ose as possible to the ic control system ground (the gnd1 pin). 7. hall input signals signals with an amplitude in excess of the hysteresis (42m v maximum) must be provided as the hall input signals. however, an amplitude of over 100mv is desirable to minimize the influence of noise. if the output waveforms are disturbed (at phase switching) due to noise on the ha ll inputs, insert capacitors across these inputs. 8. fg input signal normally, one phase of the hall signals is input as the fg si gnal. if noise is a problem the input must be filtered with either a capacitor or an rc filter circuit. although it is also possible to remove fg signal noise by inserting a capacitor between the fgfil pin and ground, the ic may not be able to operate correctly if this signal is damped excessively. if this capacitor is used, its value must be less than about 2200pf. if the location of this capacitor's ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. thus the ground lead location must be chosen carefully. 9. rotor constraint protection circuit this ic provides a rotor constraint protection circuit to protect the ic itself and the motor when the motor is constrained. if the ld output is high (unlocked) for over a certain fixed period with the ic in the start state, the low side transistor will be turned off. the time constant is determined by the capacitor connected to the csd pin. 120 c ( f) if a 0.068 f capacitor is used, the protection time will be about 8 seconds. the set time must be selected to have an adequate margin with respect to the motor startup time. this protection circuit will not operate during deceleration when the clock frequency is switched. to clear the rotor cons traint protection state, the ic must be set to the stopped state or the power must be turned off and reapplied. since the csd pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the reset state and the ic will not be able to function if th is pin is connected to groun d. therefore, both a 220k resistor and a 4700pf capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not used.
LB11870 no.7256-13/14 10. phase lock signal (1) phase lock range since this ic does not include a counter or similar func tionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by ic characteristics. (this is because the acceleration of the changes in the fg frequency influen ces the range.) when it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring th e actual motor state. since speed errors occur easily in states where the fg acceleration is large, it is thought that the speed errors w ill be the largest du ring lock pull-in at startup and when unlocked du e to switching clock frequencies. (2) masking function for the phase lock state signal a stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. however, this results in the lock state signal output being delayed by the masking time. the masking time is determined by the capac itor inserted between the cld pin and ground. 0.9 c ( f) when a 0.1 f capacitor is used, the masking time will be about 90ms. in cases where complete masking is required, a masking time with fully adequate margin must be used. if no masking is required, leave the cld pin open. 11. power supply stabilization since this ic provides a large output cu rrent and adopts a switching drive technique, the power supply line level can be disrupted easily. thus capacitors large enough to stab ilize the power supply voltage must be inserted between the v cc pins and ground. the ground leads of these capacitors must be connected to the three pins that are the power grounds, and they must be co nnected as close as possible to the pins th emselves. if these capacitors (electrolytic capacitors) cannot be connected close to their co rresponding pins, ceramic capacitors of about 0.1 f must be connected near these pins. if reverse torque control mode is selected for use during de celeration, since there are stat es where power is returned to the power supply system, the power supply line levels w ill be particularly easily disrupted. since the power line level is most easily disrupted during lock pull-in at high mo tor speeds, this state needs extra attention; in particular, capacitors that are adequately large to handle this situation must be selected. if diodes are inserted in the power supply lines to prevent destruction of the device if th e power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. 12. vreg stabilization a capacitor of at least 0.1 f must be used to stabilize the vreg voltage , which is the control circuit power supply. the ground lead of that capacitor must be connected as close as possible to the ic control system ground (gnd1). 13. error amplifier external component values to prevent adverse influence from noise, the error amplifier external components must be located as close to the ic as possible. in particular, they must be located as far from the motor as possible. 14. frame pin and the ic metallic rear surface the frame pin must be connected to the gnd1 and gnd2 pins, and the ground side of the electrolytic capacitor must be connected to gnd3. the ic's metallic rear surface is connected to the frame pin internally to the ic. thermal dissipation can be improved si gnificantly by tightly bo nding the metallic surface of the back of the ic package to the pcb with, fo r example, a solder with good thermal conductivity.
LB11870 no.7256-14/14 ps this catalog provides informati on as of june, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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